`include "defines.v"
module ysyx_210448_wb_stage (
  input wire clk,
  input wire rst,
  input wire ld,
  input wire [63:0] if_pc,
  input wire [31:0] wb_inst,
  input wire exe_pc_write,
  input wire [63:0] exe_pc_add,
  input wire clint_skip,
  input wire id_ena1,
  input wire id_ena2,
  input wire if_fetched,
  input wire wb_fetched,
  input wire exe_fetched,
  input wire mem_fetched,
  input wire mem_read,
  input wire exe_w_ena,
  input wire if_ar_hand,
  input wire axi_mem_read,
  input wire axi_mem_write,
  input [63:0] mtimecmp_data,
  input mtimecmp_open,
  input [63:0] mtime_data,
  input mtime_open,
  input wire [4:0] id_rs1,
  input wire [4:0] id_rs2,
  input wire if_w_ena,
  input wire wb_open,
  input wire [63:0]wb_pc,
  input wire wb_w_ena,
	input wire [4:0] wb_rd,
	input wire [`REG_BUS] wb_data,
  input wire wb_read,
  input wire wb_close,
  input wire [63:0]wb_read_data,
  input wire [11:0]wb_csr,
  input wire [11:0] id_csr,
  input wire wb_csr_write,
	input wire id_csr_read,
  input wire [63:0] wb_csr_data,
  output wire [63:0] id_op1,
  output wire [63:0] id_op2,
  output wire [63:0]id_t,
  output wire [`REG_BUS] regs_o[0 : 31],
  output reg [63:0] mstatus,
  output reg [63:0] sstatus,	
  output reg [63:0] mepc,
  output wire [63:0] mtvec,
  output reg [63:0] mcause,
  output reg [63:0] mhartid,
	output reg [63:0] mip,
	output reg [63:0] mie,
  output wire [63:0] mcycle,
  output reg [63:0]mscratch,
  output id_csr_skip,
  output reg [63:0] mcause_data,
  output reg [63:0] mstatus_data,
  output reg [63:0] rmstatus,
  output wire [63:0] csr_pc_add,
  output wire csr_pc_write,
	output wire wb_ok,
  output wire ena1,
  output wire ena2,
  output wire clock_interrupt
);

wire [63:0] mtimecmp;
wire [63:0] mtime;
wire w_ena;
wire [4:0] w_rd;
assign w_rd=(w_ena)?wb_rd:0;
//wire ena1;
assign ena1=(axi_mem_write)?((wb_rd==id_rs1)?((if_w_ena==1'b1)?0:id_ena1):id_ena1):((wb_rd==id_rs1)?((exe_w_ena==1'b1)?id_ena1:0):id_ena1);
assign ena2=(axi_mem_write)?((wb_rd==id_rs2)?((if_w_ena==1'b1)?0:id_ena2):id_ena2):((wb_rd==id_rs2)?((exe_w_ena==1'b1)?id_ena2:0):id_ena2);
//数据冒险结束的标志
assign wb_ok=(wb_open==1'b1|wb_close==1'b1)?1'b1:1'b0;
assign w_ena=(axi_mem_read)?wb_read:wb_w_ena;

ysyx_210448_CSR ysyx_210448_CSR(
.clk(clk),
.rst(rst),
.if_pc(if_pc),
.wb_inst(wb_inst),
.if_ar_hand(if_ar_hand),
.exe_pc_write(exe_pc_write),
.exe_pc_add(exe_pc_add),
.exe_fetched(exe_fetched),
.wb_csr(wb_csr),
.id_csr(id_csr),
.pc(wb_pc),
.mem_fetched(mem_fetched),
.mem_read(mem_read),
.wb_read(wb_read),
.if_fetched(if_fetched),
.wb_fetched(wb_fetched),
.wb_csr_write(wb_csr_write),
.id_csr_read(id_csr_read),
.csr_data(wb_csr_data),
.id_t(id_t),
.id_rs1(id_rs1),
.wb_rd(wb_rd),
.mstatus_data(mstatus_data),
.mtimecmp_data(mtimecmp_data),
.mtimecmp_open(mtimecmp_open),
.mtime_data(mtime_data),
.mtime_open(mtime_open),
.clint_skip(clint_skip),
.mcycle(mcycle),
.mstatus(mstatus),
.sstatus(sstatus),	
.mhartid(mhartid),
.clock_interrupt(clock_interrupt),
.mepc(mepc),
.mtvec(mtvec),
.mcause(mcause),
.mip(mip),
.mie(mie),
.id_csr_skip(id_csr_skip),
.mcause_data(mcause_data),
.csr_pc_add(csr_pc_add),
.csr_pc_write(csr_pc_write),
.mtime(mtime),
.mtimecmp(mtimecmp),
.mscratch(mscratch),
.rmstatus(rmstatus)
);

  ysyx_210448_regfile ysyx_210448_Regfile(
  .clk(clk),
  .rst(rst),
  .ld(ld),
  .read(wb_read),//wb_read
  .read_data(wb_read_data),
  .w_addr(w_rd),
  .data(wb_data),
  .w_ena(w_ena),
  .rs1(id_rs1),
  .op1(id_op1),
  .ena1(ena1),
  .rs2(id_rs2),
  .op2(id_op2),
  .ena2(ena2),
  .regs_o(regs_o)
);

endmodule

